View MSC23V26457TA-XXBS8_1284231.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

in im el Pr
Semiconductor MSC23V26457TA-XXBS8/ MSC23V26457SA-xxBS8
Semiconductor
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
y ar
2,097,152-Word 64-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The Oki MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8 is a fully decoded 2,097,152-word 64-bit CMOS dynamic random access memory composed of eight 16-Mb DRAMs (2M 8) in TSOP or SOJ packages mounted with decoupling capacitors on an 168-pin glass epoxy DIMM Package supports any application where high density and large capacity of storage memory are required.
FEATURES
* 2,097,152-word 64-bit (8 Byte) organization * 168-pin DIMM MSC23V26457TA-XXBS8 : TSOP type MSC23V26457SA-xxBS8 : SOJ type * Single 3.3 V supply 0.3 V tolerance * Input : LVTTL compatible * Output : LVTTL compatible, 3-state, nonlatch * Refresh : 2048 cycles/32 ms * CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability * Multi-bit test mode capability * Fast Page Mode with EDO capability * Serial Presence Detect
PRODUCT FAMILY
Family MSC23V26457TA-60BS8 MSC23V26457SA-60BS8 MSC23V26457TA-70BS8 MSC23V26457SA-70BS8 Access Time (Max.) tRAC tAA tCAC tOEA Power Dissipation Cycle Time Operating (Max.) Standby (Max.) (Min.) 110 ns 130 ns 4320 mW 28.8 mW 70 ns 35 ns 20 ns 20 ns 3744 mW
8
60 ns 30 ns 15 ns 15 ns
631
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
Semiconductor
PIN CONFIGURATION
MSC23V26457TA-XXBS8
(Unit : mm) *1 133.35 0.2 2 - R2 0.1 2.67 Max.
25.4 0.13
17.78 0.13
3.0 0.13
2 - 3 0.1 A 11.43 0.1 36.83 0.1 45.18 0.13 127.35 Typ. B 2 - R1 0.1 54.61 0.1 1.27 0.1 84 6.0 Min.
5.89 0.13 21.495 0.13 3.0 0.13
CL
1.0 0.1 0.25 Max.
3.00 0.13
3.00 0.13
2.0 0.1 6.35 0.1 DETAIL A
2.0 0.1 6.35 0.1 DETAIL B
0.23 Min. 1.27 0.1
8
*1 The common size difference of the board width 19.78 mm of its height is specified as 0.2. The value above 19.78 mm is specified as 0.5.
632
Semiconductor MSC23V26457SA-xxBS8
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
(Unit : mm) *1 133.35 0.2 2 - R2 0.1 5.28 Max.
25.4 0.13
17.78 0.13
3.0 0.13
2 - 3 0.1 A 11.43 0.1 36.83 0.1 45.18 0.13 127.35 Typ. B 2 - R1 0.1 54.61 0.1 1.27 0.1 84 6.0 Min.
5.89 0.13 21.495 0.13 3.0 0.13
CL
1.0 0.1 0.25 Max.
3.00 0.13
3.00 0.13
2.0 0.1 6.35 0.1 DETAIL A
2.0 0.1 6.35 0.1 DETAIL B
0.23 Min. 1.27 0.1
*1 The common size difference of the board width 19.78 mm of its height is specified as 0.2. The value above 19.78 mm is specified as 0.5.
8
633
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
Semiconductor
Front Side
Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Pin No. Pin Name 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VCC DQ14 DQ15 NC NC VSS NC NC VCC WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 Pin No. Pin Name 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 A4 A6 A8 A10R NC VCC VCC NC VSS OE2 RAS2 CAS2 CAS3 WE2 VCC NC NC Pin No. Pin Name 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 NC NC VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS Pin No. Pin Name 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VCC
Back Side
Pin No. Pin Name 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 Pin No. Pin Name 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 VCC DQ46 DQ47 NC NC VSS NC NC VCC NC CAS4 CAS5 NC NC VSS A1 A3 Pin No. Pin Name 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 A5 A7 A9 NC NC VCC NC NC VSS NC NC CAS6 CAS7 NC VCC NC NC Pin No. Pin Name 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 NC NC VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS Pin No. Pin Name 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC
8
634
Semiconductor Serial PD Matrix
Byte Number 0 1 2 3 4 5 6 7 8 9 (-60) 9 (-70) 10 (-60) 10 (-70) 11 12 Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Bit 4 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
Bit 3 1 1 0 1 1 0 0 0 0 1 0 1 0 0 0
Bit 2 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0
Bit 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 0
Bit 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0
Remark Number of Bytes used (13 Bytes) Total SPD Memory size (256 Bytes) Memory type (EDO) Number of Rows (11) Number of Columns (10) Number of Banks (1) Module Data Width (64) Module Data Width Continued (0) Supply Voltage (3.3 V, LVTTL) RAS Access Time (60 ns) RAS Access Time (70 ns) CAS Access Time (15 ns) CAS Access Time (20 ns) Non parity Normal Refresh
8
635
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
Semiconductor
BLOCK DIAGRAM
A0 - A9 A10R RAS0 WE0 OE0 CAS0 A0 - A9 A10R RAS CAS WE OE VCC A0 - A9 A10R RAS CAS1 CAS WE OE VCC A0 - A9 A10R RAS CAS2 CAS WE OE VCC A0 - A9 A10R RAS CAS3 CAS WE OE VCC
DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
RAS2 WE2 OE2 CAS4 A0 - A9 A10R RAS CAS WE OE VCC
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
VSS
DQ DQ DQ DQ DQ DQ DQ DQ
VSS
DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
A0 - A9 A10R RAS CAS5 CAS WE OE VCC
VSS
DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
VSS
DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
A0 - A9 A10R RAS CAS6 CAS WE OE VCC
VSS
DQ DQ DQ DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
VSS
DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
A0 - A9 A10R RAS CAS7 CAS WE OE VCC
8
VSS
VSS
VCC C1 VSS C8 SCL SDA SCL SDA A0 A1 A2 Serial PD
SA0 SA1 SA2
636
Semiconductor
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Voltage VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD Topr Tstg Rating -0.5 to 4.6 -0.5 to 4.6 50 8 0 to 70 -40 to 125 Unit V V mA W C C
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions
(Ta = 0C to 70C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 -0.3 Typ. 3.3 0 -- -- Max. 3.6 0 VCC + 0.3 0.8 Unit V V V V
Capacitance
(Ta = 25C, f = 1 MHz) Parameter Input Capacitance (A0 - A9, A10R) Input Capacitance (RAS0, RAS2, WE0, WE2, OE0, OE2) Input Capacitance (CAS0 - CAS7) I/O Capacitance (DQ0 - DQ63) Symbol CIN1 CIN2 CIN3 CDQ Typ. -- -- -- -- Max. 49 35 13 13 Unit pF pF pF pF
8
Note : Capacitance measured with Boonton Meter.
637
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
Semiconductor
DC Characteristics
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Parameter
Symbol
Condition 0 V VI VCC + 0.3 V;
-60 Min. -80 Max. 80 Min. -80
-70 Max. 80
Unit Note
Input Leakage Current
ILI
All other pins not under test = 0 V DOUT disable 0 V VO 3.6 V IOH = -2.0 mA IOL = 2.0 mA RAS, CAS cycling, tRC = Min. RAS, CAS = VIH
A
Output Leakage Current Output High Voltage Output Low Voltage Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode)
ILO VOH VOL ICC1
-10 2.4 0 -- -- --
10 VCC 0.4 1200 16 8
-10 2.4 0 -- -- --
10 VCC 0.4 1040 16 8
A V V mA 1, 2 mA mA 1 1
ICC2
RAS, CAS VCC -0.2 V RAS cycling,
ICC3
CAS = VIH, tRC = Min. RAS cycling,
--
1200
--
1040
mA 1, 2
ICC6
CAS before RAS, tRC = Min. RAS = VIL,
--
1200
--
1040
mA 1, 2
ICC7
CAS cycling, tHPC = Min.
--
1200
--
1040
mA 1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition. 2. Address can be changed once or less while RAS=VIL. 3. Address can be changed once or less while CAS=VIH.
8
638
Semiconductor AC Characteristics (1/2)
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Output Hold Time from CAS Low CAS to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time CAS Pulse Width RAS Low to CAS High Delay Time CAS High to RAS Low Delay Time RAS Hold Time from CAS Precharge CAS, OE Hold Time (Output Disable) RAS to CAS Delay Time RAS to Column Address Delay Time RAS to Second CAS Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time
Symbol
Note 1,2,3,12,13 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 7, 8 7, 8 7 7 3 4, 5, 6 4, 5 4, 6 4 4 4
-60 Min. 110 150 25 80 -- -- -- -- -- 0 5 0 0 0 0 3 -- 40 60 60 15 15 10 15 40 5 35 5 20 15 60 0 10 0 15 40 30 Max. -- -- -- -- 60 15 30 35 15 -- -- 15 15 15 15 50 32 -- 10k 100k -- -- -- 10k -- -- -- -- 45 30 -- -- -- -- -- -- -- Min. 130 180 30 95 -- -- -- -- -- 0 5 0 0 0 0 3 -- 50 70 70 20 20 10 20 45 5 40 10 20 15 70 0 10 0 15 45 35
-70 Max. -- -- -- -- 70 20 35 40 20 -- -- 15 15 15 15 50 32 -- 10k 100k -- -- -- 10k -- -- -- -- 50 35 -- -- -- -- -- -- --
tRC tRWC tHPC tRAC tCAC tAA tCPA tOEA tCLZ tDOH tCEZ tREZ tOEZ tWEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tCHO tRCD tRAD tRSCD tASR tRAH tASC tCAH tAR tRAL
Fast Page Mode Read Modify Write Cycle Time tPRWC
8
639
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
Semiconductor
AC Characteristics (2/2)
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width WE Low to OE Low Delay Time OE Precharge Time OE Low to CAS High Delay Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge to WE Delay Time -60
Symbol
Note 1,2,3,12,13 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 10 11 11 9 9 10
-70 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0 0 0 0 15 45 15 10 20 10 10 20 20 0 15 45 15 45 60 95 65 5 5 15 10 10 10 10 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Min. 0 0 0 0 10 40 10 5 15 10 10 15 15 0 15 40 15 35 50 80 55 5 5 10 10 10 10 10
tRCS tRCH tRRH tWCS tWCH tWCR tWP tOEH tOEP tOCH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD
Write Command Pulse Width (Output Disable) tWPE
CAS Active Delay Time from RAS Precharge tRPC RAS to CAS Set-up Time (CAS before RAS) tCSR RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) tCHR tWRP tWRH tWTS tWTH
8
WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode)
640
Semiconductor Notes:
MSC23V26457TA-XXBS8/MSC23V26457SA-xxBS8
1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.) the cycle is an early write cycle and the data output pin will remain in a high impedance state throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), the cycle is a read modify write cycle and the data output pin will contain data read from the selected cell. If neither conditions is satisfied, the data output logic state (at access time) is undefined. 11. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in an OE control write cycle or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In the test mode CA9 is not used and each DQ pin now accesses 2 bit locations. In a read cycle, if the 2 data bits are equal, the DQ pin will indicate a high level. If the 2 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values.
8
See ADDENDUM K for AC Timing Waveforms
641

▲Up To Search▲

Price & Availability of MSC23V26457TA-XXBS8

	To Download MSC23V26457TA-XXBS8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .